/*
 * SPDX-License-Identifier: Apache-2.0
 *
 * Offsets for the Power, Reset, and Clock Management module
 * registers, in the CC2650 System on Chip.
 */


#ifndef _CC2650_PRCM_H_
#define _CC2650_PRCM_H_

/* Registers */

enum CC2650_PRCM_Registers {
	CC2650_PRCM_CLKLOADCTL = 0x28,
	CC2650_PRCM_SECDMACLKGR = 0x3C,
	CC2650_PRCM_GPIOCLKGR = 0x48,
	CC2650_PRCM_UARTCLKGR = 0x6C,
	CC2650_PRCM_UARTCLKGS = 0x70,
	CC2650_PRCM_UARTCLKGDS = 0x74,
	CC2650_PRCM_PDCTL0 = 0x12C,
	CC2650_PRCM_PDSTAT0 = 0x140
};


/* Register-specific bits */

/* CLKLOADCTL */
enum CC2650_PRCM_CLKLOADCT_POS {
	CC2650_PRCM_CLKLOADCTL_LOAD_POS = 0,
	CC2650_PRCM_CLKLOADCTL_LOAD_DONE_POS = 1
};

enum CC2650_PRCM_CLKLOADCTL_MASK {
	CC2650_PRCM_CLKLOADCTL_LOAD_MASK      = 0x00000001,
	CC2650_PRCM_CLKLOADCTL_LOAD_DONE_MASK = 0x00000002
};

/* SECDMACLKGR */
enum CC2650_PRCM_SECDMACLKGR_POS {
	CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_POS = 1
};

enum CC2650_PRCM_SECDMACLKGR_MASK {
	CC2650_PRCM_SECDMACLKGR_TRNG_CLK_EN_MASK = 0x00000002
};

/* GPIOCLKGR */
enum CC2650_PRCM_GPIOCLKGR_POS {
	CC2650_PRCM_GPIOCLKGR_CLK_EN_POS = 0
};

enum CC2650_PRCM_GPIOCLKGR_MASK {
	CC2650_PRCM_GPIOCLKGR_CLK_EN_MASK = 0x00000001
};

/* UARTCLKGR */
enum CC2650_PRCM_UARTCLKGR_POS {
	CC2650_PRCM_UARTCLKGR_CLK_EN_POS = 0
};

enum CC2650_PRCM_UARTCLKGR_MASK {
	CC2650_PRCM_UARTCLKGR_CLK_EN_MASK = 0x00000001
};

/* UARTCLKGS */
enum CC2650_PRCM_UARTCLKGS_POS {
	CC2650_PRCM_UARTCLKGS_CLK_EN_POS = 0
};

enum CC2650_PRCM_UARTCLKGS_MASK {
	CC2650_PRCM_UARTCLKGS_CLK_EN_MASK = 0x00000001
};

/* UARTCLKGDS */
enum CC2650_PRCM_UARTCLKGDS_POS {
	CC2650_PRCM_UARTCLKGDS_CLK_EN_POS = 0
};

enum CC2650_PRCM_UARTCLKGDS_MASK {
	CC2650_PRCM_UARTCLKGDS_CLK_EN_MASK = 0x00000001
};

/* PDCTL0 */
enum CC2650_PRCM_PDCTL0_POS {
	CC2650_PRCM_PDCTL0_SERIAL_ON_POS = 1,
	CC2650_PRCM_PDCTL0_PERIPH_ON_POS = 2
};

enum CC2650_PRCM_PDCTL0_MASK {
	CC2650_PRCM_PDCTL0_SERIAL_ON_MASK = 0x00000002,
	CC2650_PRCM_PDCTL0_PERIPH_ON_MASK = 0x00000004
};

/* PDSTAT0 */
enum CC2650_PRCM_PDSTAT0_POS {
	CC2650_PRCM_PDSTAT0_RFC_ON_POS = 0,
	CC2650_PRCM_PDSTAT0_SERIAL_ON_POS = 1,
	CC2650_PRCM_PDSTAT0_PERIPH_ON_POS = 2
};

enum CC2650_PRCM_PDSTAT0_MASK {
	CC2650_PRCM_PDSTAT0_RFC_ON_MASK    = 0x00000001,
	CC2650_PRCM_PDSTAT0_SERIAL_ON_MASK = 0x00000002,
	CC2650_PRCM_PDSTAT0_PERIPH_ON_MASK = 0x00000004
};

#endif /* _CC2650_PRCM_H_ */
